The DM9106 is a fully integrated, high performance, and cost-effective fast Ethernet switch controller with one general PCI bus interface, two ports 10M/100Mbps PHY, and one port MII or RMII interface. The general PCI bus connects directly to internal host MAC with 32-bit data registers and internal memory. The host MAC has the similar functions as other 10/100Mbps PHY or MII does. This makes the DM9106 act as an extended four ports switch and to shorten the latency from PCI port to destination port. The internal memory of the DM9106 supports up to 1K uni-cast MAC address table, and provides to three ports’ and PCI port’s transmit and receive buffers. For efficient memory usage algorithm, if application only uses two ports solution, the another disabled port’s memory resource can be shared to other two ports and PCI port.

• Ethernet Switch with two 10/100Mb PHY, one MII/RMII, and PCI bus interface
• ‰Support Reverse-MII
• PCI bus master architecture
• EEPROM interface for power up configurations
• Support TCP/UDP/IPv4 checksum offload
• Support HP Auto-MDIX
• Support IEEE 802.3x Flow Control in Full-duplex mode
• Support Back Pressure Flow Control in Half-duplex mode
• Per port support 4 priority queues by Port-based, 802.1P QoS, and IP TOS priority
• Support 802.1Q VLAN up-to 16 VLAN group
• Support VLAN ID tag/untag options
• Per port support bandwidth, ingress and egress rate control
• Support Broadcast Storming filter function
• Support Store and Forward switching approach
• Support up-to 1K Uni-cast MAC addresses
• Support MIB counters for diagnostic
• Support IGMP Snooping v1, v2
• EEPROM 93C46 or 93C56 auto detection
• PCI bus driving capability adjustable
• Port 2 TXD/TXE driving capability adjustable
• 128-pin LQFP 1.8V internal core, 3.3V I/O with 5V tolerant

Each port of the DM9106 provides four priority transmit queues, that can be defined by port-based, 802.1p VLAN, or IP packet ToS field automatically, to fit the various bandwidth and latency requirement of data, voice, and video applications. Each port also supports ingress and/or egress rate control to provide proper bandwidth. And up to 16 groups of 802.1Q VLAN with Tag/Un-tag functions are supported to provide efficient packet forwarding. The TCP/UDP/IPv4 checksum generation and checking functions are also provided by PCI port to offload the processor computing loading. Besides the packet transmit and receive functions, the PCI port also provides various registers to control and get status of the DM9106 functional operation. Each port, including the PCI port, provides the MIB counters and loop-back capability and the build in memory self test (BIST) for system and board level diagnostic. The integrated two ports PHY are compliant with IEEE 802.3u standards. The MII interface provides the flexibility to connect Ethernet PHY, and it can be configured as Reversed MII interface for SoC with MII interface. An alternative interface, the RMII interface, is also provided to connect the lower pin count Ethernet PHY or SoC with RMII interface.